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STN LCD Driver
MN863831EFS
320-Output STN Segment Driver
I Overview
The MN863831EFS is a 320-output segment driver IC for dot matrix STN LCD panels. It latches 4-bit or 8-bit parallel data transferred from an LCD controller and generates the LCD drive signals. In combination with an LCD common driver IC, MN86372 series, this IC is optimal for implementing low-power LCD modules. Since this IC also provides an LCD drive voltage compensation function, it can implement high-quality LCD display modules with minimal crosstalk. It supports both color and monochrome displays.
I Features
* Supports LCD drive voltages up to 6.0 V. * Provides 320 LCD drive outputs. * Provides an LCD drive voltage compensation function to implement high-quality LCD display modules with minimal crosstalk. * Inverts the LCD drive voltage by signal alternation. * Provides 5 LCD drive voltage input pins: VHC, VH, VM, VL, and VLC * Built-in voltage conversion block (level shifter) allows interfacing with LCD controllers with supply voltages in the range from 2.5 V to 5.5 V. * Built-in bidirectional shift register allows arbitrary direction of the output data transfer and allows easy mounting in large-screen applications. * Supports multistage cascade connection to drive high-resolution LCD panels. * Supports both 4-bit and 8-bit parallel input mode. * The 4-bit and 8-bit parallel input modes allow data rates 1/4 or 1/8 of those required with conventional serial transfer devices for lower power consumption. * Provides a power saving function, in which all but one driver are set to standby mode and disable to input display data, for even lower power consumption in LCD modules with multistage cascade connection.
* Word processors, PDAs, and other portable information terminals
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I Applications
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Publication date: May 2002
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MN863831EFS
I Block Diagram
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VHC VH VM VL VLC /DISPOFF CL1 CL2
5-level analog switch
320 Control circuit Level shifter
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LP
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VDD VSS
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Enable control
DF
DF latch (1)
DF latch (2)
******************** 320-bit data latch (2)
80 x 4-bit, 40 x 8-bit bidirectional shift register 8 Data selector 8
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2
CP SHL MOD
/EL
/ER
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D0 to D7
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Level shifter 320-bit data latch (1)
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320
O320
O1
MN863831EFS
I Pin Arrangement
The view from pattern surface (copper printing pattern)
Film Chip
Film
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Outputs (320 pins)
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O316 O317 O318 O319 O320
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O1 O2 O3 O4 O5
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VLC VL VM VH VHC VSS MOD /EL DF CL1 CL2 LP CP D7 D6 D5 D4 D3 D2 D1 D0 /DISPOFF /ER SHL VDD VHC VH VM VL VLC
Inputs (30 pins)
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MN863831EFS
I Pin Descriptions
Pin No. D0 to D7 I/O I Function Display data inputs (8 bits) Description Parallel input of display data in 4-bit or 8-bit units. * In 4-bit parallel input mode, the 4 pins D0 to D3 are used for data input. The 4 pins D0 to D7 should be tied to VDD or VSS. * In 8-bit parallel input mode, the 8 pins D0 to D7 are used for data input. These pins output the LCD drive voltages. Switches the shift register data shift direction, and the /ER and /EL pin I/O mode. The shift register transfer clock input. The shift register operates on the falling edge of this signal.
O1 to O320 SHL CP LP /DISPOFF CL1 CL2 DF VDD VSS VH (2 pins) VL (2 pins) VM (2 pins)
O I I I I I I I Power supply Power supply Power supply Power supply Power supply
LCD drive outputs Shift direction selection Shift clock input Latch signal input Display off input
LCD compensation voltage Controls the period for the LCD compensation voltage (VHC and VLC) (VHC and VLC) control output to the LCD drive output pins according to the display data. LCD compensation voltage (VM) control Alternation signal input
Logic system power supply Power supply used for the logic circuits GND GND
Drive power supply Drive power supply
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Mode selection
Drive power supply Drive power supply
VHC (2 pins) Power supply VLC (2 pins) Power supply /EL /ER MOD I/O I/O I
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Drive power supply Enable signal input and output Enable signal input and output
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MOD Low High
Controls the period for the LCD compensation voltage (VM) output to the LCD drive output pins according to the display data.
Performs signal alternation for the LCD drive voltage.
LCD drive power supply
LCD drive power supply LCD drive power supply, (LCD compensation power supply) LCD drive power supply, (LCD compensation power supply) Used as the power supply for the LCD drive circuit. LCD drive power supply, (LCD compensation power supply) Connected internally to the VSS pin. Data input/output for the chip enable signal Data input/output for the chip enable signal
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4-bit parallel input 8-bit parallel input
The LCD drive outputs output the VM level regardless of the data while this pin is low.
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The DF signal and the shift register data are latched on the falling edge of this signal, and the latched data is output.
MN863831EFS
I Function Descriptions
1. Control circuit for bidirectional shift register This IC includes two circuits, an enable control circuit and a data selector, that control the built-in bidirectional shift register. 1.1 Enable control circuit This circuit consists of a base-80 counter circuit (for 4-bit parallel input mode), a base-40 counter circuit (for 8-bit parallel input mode), and a control circuit for the chip enable I/O circuit. This counter counts clock pulses and outputs a carry on the falling edge of the 80th clock cycle (in 4-bit parallel input mode) or the 40th clock cycle (in 8-bit parallel input mode). This corresponds to the completion of the shift register data shift operation. This carry stops the data shift clock internally to the IC, and places the counter and the shift register in the stopped state. When LP signal goes high, the base-80 and base-40 counters are reset and set to the counter wait state (standby state). The standby state is not cleared until the chip enable I/O signal (/EL and /ER) that corresponds to shift direction goes low. When that chip enable signal goes low, the data shift clock and counter start operating again. When this IC is connected in the serial cascade form, the counter carry signal is used as the chip enable signal for the driver IC in the next stage. The result of this operation is that at the completion of each 80 clock cycles (in 4-bit parallel input mode) or 40 clock cycles (in 8-bit parallel input mode), the next driver IC in sequence goes to the active state and the total power consumption of the whole LCD panel is reduced. 1.2 Data selector circuit This circuit determines, based on the state of the SHL pin, the data shift direction of the internal shift register and the I/O mode of the chip enable I/O pin as shown in tables 1-a and 1-b. 2. 80 x 4-bit (4-bit parallel input mode)/40 x 8-bit (8-bit parallel input mode) bidirectional shift register The IC internal 4-bit parallel 80-stage and 8-bit parallel 40-stage bidirectional shift registers operate on the falling edge of the clock pulse. In 4-bit parallel input mode, since the input data is divided into 4-bit parallel units, the shifting of the 320 output units of data requires 80 clock cycles. (See Timing Charts 1 and 3.) In 8-bit parallel input mode, since the input data is divided into 8-bit parallel units, the shifting of the 320 output units of data requires 40 clock cycles. (See Timing Charts 2 and 4.) The shift direction is selected by the SHL pin as shown in tables 1-a and 1-b. 3. 320-bit data latch (2) The 320-bit data latch (2) holds the 320 bits of data acquired by the shift register for a single horizontal scan period (1H). Data is latched on the falling edge of the LP signal, which is the start pulse for the horizontal scan period, held for 1H, and the next data is latched on the next falling edge on the LP signal. Timing Chart 3 shows the shift register and latch operation for the first stage segment driver when multiple driver ICs are connected in series and operated in 4-bit parallel mode. Also, Timing Chart 4 shows the shift register and latch operation for the first stage segment driver when multiple driver ICs are connected in series and operated in 8-bit parallel mode.
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MN863831EFS
I Function Descriptions (continued)
4. Level shifters The level shifters convert levels from the logic circuit signal levels (VDD = high, VSS = low) to the signal levels (VHC = high, VLC = VSS = low) used by the LCD drive circuits, such as the analog switches. The IC includes two types of level shifters, one is for 320 bits display data and the other is for control signals. 5. 320-bit data latch (1) The 320-bit data latch (1) holds the 320 bits of display data acquired by the 320-bit data latch (2) for an additional 1H. Thus the 320-bit data latch (1) holds the data for the previous line from the display data currently being scanned. Data is latched on the falling edge of the LP signal, held for 1H, and the next data is latched on the next falling edge on the LP signal. 6. 5-level analog switch The 5-level analog switch is controlled by the control circuit and selects one of the 5 drive voltages (VHC, VH, VM, VL, and VLC), and outputs the selected levels to the 320 LCD drive output pins. 7. DF latch (1) The DF latch (1) holds the DF data for a single horizontal scan period (1H). Data is latched on the rising edge of the LP signal, which is the start pulse for the horizontal scan period, held for 1H, and the next data is latched on the next rising edge on the LP signal. 8. DF latch (2) The DF latch (2) latches the data acquired by the DF latch (1) on the falling edge of the LP signal, holds that data for 1H, and latches the next data on the next falling edge of the LP signal. (Timing Charts 3 and 4 show this latch operation.) 9. Control circuit The voltage selected by the 5-level analog switch is determined by the 320-bit data latch (1), the 320-bit data latch (2), the /DISPOFF signal, the CL1 signal, the CL2*LP signal, the DF input, and DF latch (2). When the /DISPOFF signal is low, the VM level of the LCD drive voltage is selected, regardless of the values of the data latches (1) and (2) outputs, the DF input, the DF latch (2) output, and the high/low state of the CL1 and CL2*LP signals. When the /DISPOFF signal is low, the VM level is output from the common driver, and the voltage applied to all of the dots becomes 0 V, since the same voltage is applied. This results in a completely blank display. When either the CL1 or CL2*LP signal is high, the IC switches the LCD drive voltage and the LCD compensation voltage by comparing the data latch (1) and (2) outputs with the DF input and the DF latch (2) output. Table 2 lists the LCD drive output pin output voltage levels according to the data latch (1) output (Qn-1), the data latch (2) output (Qn), the CL1 and CL2*LP signals, the DF input, the DF latch (2) output (DFn-1), and the /DISPOFF signal. Figure 1 presents examples of the LCD drive output pin waveform as driven according to table 2, which appears later. Two examples are presented, one with the DF pin held high, and the other with an LCD alternation signal input to the DF pin.
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I Function Descriptions (continued)
Table 1-a. Data shift control SHL Low /ER Input /EL 1 Output D3 D2 D1 D0 High Output Input D3 D2 D1 D0 2 O320 O316 O319 O315 O318 O314 O317 O313 O1 O2 O3 O4 O5 O6 O7 O8 In 4-bit parallel input mode (MOD = low) Shift clock *** n *** O4(80-n)+4 *** O4(80-n)+3 *** O4(80-n)+2 *** O4(80-n)+1 *** O4n -3 *** O4n -2 *** O4n -1 *** O4n *** 79 *** O8 *** O7 *** O6 *** O5 80 O4 O3 O2 O1
*** O313 O317 *** O314 O318 *** O315 O319 *** O316 O320
Table 1-b. Data shift control SHL Low /ER Input /EL 1 Output D7 D6 D5 D4 D3 D2 D1 2 O240 O232 O239 O231 O238 O230 O237 O229 O236 O228 O235 O227 O234 O226 O233 O225 O9 O10 O11 O12 O13 O14 O15 O16
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*** O8n
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Shift clock *** n *** O8(40-n)+8 *** O8(40-n)+7 *** O8(40-n)+6 *** O8(40-n)+5 *** O8(40-n)+4 *** O8(40-n)+3 *** O8(40-n)+2 *** O8(40-n)+1 *** O8n-7 *** O8n-6 *** O8n-5 *** O8n-4 *** O8n-3 *** O8n-2 *** O8n-1
In 8-bit parallel input mode (MOD = high) *** 39 *** O16 *** O15 *** O14 *** O13 *** O12 *** O11 *** O10 *** O9 40 O8 O7 O6 O5 O4 O3 O2 O1
High
Output
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Input D7 D6 D5 D4 D3 D2 D1 D0
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D0 O1 O2 O3 O4 O5 O6 O7 O8
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*** O305 O313 *** O306 O314 *** O307 O315 *** O308 O316 *** O309 O317 *** O310 O318 *** O311 O319 *** O312 O320
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I Function Descriptions (continued)
Table 2. LCD drive output pin output voltage /DISPOFF High CL1 High CL2 * LP Low DF latch (2) output DFn-1 High DF input High Data latch (1) Data latch (2) LCD drive output output Qn-1 output Qn O1 to O320 High Low Low High Low Low High High Low Low High Low High Low High Low High Low High Low High Low Low Low Low High Low High Low High Low Low High Low Low High Low High Low High High Low High Low High Low High Low High Low Low Low High Low VL VHC VLC VH VHC VL VH VLC VLC VH VL VHC VH VLC VHC VL VL VM VM VH VM VL VH VM VM VH VL VM VH VM VM VL VL VH VH VL VM
Low
High
High
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High Low High
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Low
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Note) 1. : Don't care 2. The timing charts for the IC blocks are presented on the following pages. 3. The IC is specified to operate as follows: when the DF input is high, the output is inverted with respect to the actual input data. 4. To provide correct display, either the input data must be inverted, or an input to the DF pin that is inverted with respect to that of the common driver must be provided.
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Low High Low
High
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High High High
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1) With the DF pin input held at the high level 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
2) With an alternation signal input to the DF pin
1
2
3
4
5
LP
CL1
I Function Descriptions (continued)
Figure 1. LCD drive output waveform examples
CL2
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/DISPOFF
Data latch (2)
Data latch (1)
VHC
VH
VM
VL
MN863831EFS
VLC
9
10
79 80 81 160 1
I Timing Charts
1
2
3
MN863831EFS
CP
LP
/EL (first stage)
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Operating state Standby state
First stage operation
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Operating state
1. Counter and chip enable pins (4-bit parallel input mode)
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/ER (first stage)
Second stage operation Standby state
/ER (second stage)
Note) 1. When two ICs are connected in cascade (SVGA color display panel) 2. fLP = fCP /160 3. SHL = high
Note that when SHL is low, the only difference is that the /ER and /EL in input and output will be reversed. In the above timing chart, /EL becomes /ER and /ER becomes /EL. 4. MOD = low
1
2
3
39 40 41
79 80 81
120
160
200
240
1
CP
LP
/EL (first stage) Standby state
I Timing Charts (continued)
First stage operation
Operating state
/ER (first stage) Operating state
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Second stage operation
Standby state
2. Counter and chip enable pins (8-bit parallel input mode)
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/ER (second stage)
/ER (third stage)
/ER (fourth stage)
/ER (fifth stage)
/ER (sixth stage)
Note) 1. When six ICs are connected in cascade (XGA color display panel) 2. fLP = fCP /240 3. SHL = high
MN863831EFS
Note that when SHL is low, the only difference is that the /ER and /EL in input and output will be reversed. In the above timing chart, /EL becomes /ER and /ER becomes /EL. 4. MOD = high
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MN863831EFS
I Timing Charts (continued)
3. Shift register and latch operation (SVGA LCD panel)
1 CP LP SHL Low
2
3
79
80
158
159
160
Operating period
Standby period
D0
1
5
317
637
D1
2
6
318
D2
3
7
319
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Data values are fixed (the shift clock is stopped)
D3
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8
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320
Shift register output
Latch (2) output
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Data for line n-1
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Data shift in progress
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Data for line n Data for line n+1 Data for line n-1 Data for line n Latch (1) output Data for line n-2 Data for line n-1 DF DF for line n DF for line n+1 DF latch (2) output
Note) fLP = fCP /160
DF for line n-1
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638 639 640 DF for line n
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MN863831EFS
I Timing Charts (continued)
4. Shift register and latch operation (XGA LCD panel)
1 CP LP SHL Low
2
3
39
40
239
240
Operating period
Standby period
D0
1
9
313
1911
D1
2
10
314
D2
3
11
315
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Data values are fixed (the shift clock is stopped)
D5
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13
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318
D6
7
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319 320 Data for line n Data for line n-1 Data for line n-2 DF for line n DF for line n-1
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Data shift in progress
D7
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1912
1913
1918
1919
1920
Shift register output
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Data for line n-1
Data for line n+1
Latch (2) output
Data for line n
Latch (1) output
Data for line n-1
DF
DF for line n+1
DF latch (2) output
Note) fLP = fCP /240
DF for line n
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MN863831EFS
I Timing Charts (continued)
5. Segment driver LCD output waveforms
1 LP CL1 CL2 DF /DISPOFF DF latch (1) DF latch (2) O1 latch (2) output O1 latch (1) output VHC VH VM VL VLC O2 latch (2) output O2 latch (1) output VHC VH VM VL VLC
2
3
4
1
2
3
4
Low High High High High
Low
Note) The figure above shows the correspondence between the latch (1) and latch (2) data (DF latch (1) and DF latch (2)); the O1 and O2 drive voltages.
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MN863831EFS
I Timing Charts (continued)
6. Segment and common driver LCD output waveforms (when /DISPOFF is high)
1 LP CL1 CL2
2
3
4
1
2
3
4
O3
Common driver output Y1 VH VL Y2 VH VM VL Y3 VH VM VL VM
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VHC VH VM VL VLC
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O2
VHC VH VM VL VLC
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Segment driver output O1 VHC VH VM VL VLC
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MN863831EFS
I Timing Charts (continued)
7. LCD display and LCD applied voltage waveforms (when /DISPOFF is high) Segment When the drive outputs shown in section 6 are applied, if the O1 O2 O3 display is normally white, the display will be shown in the right figure. Y1 If the display is normally black, then the display will be set up (2, 1) (3, 1) (1, 1) for black/white reversed display. The waveforms of the voltages Y2 applied to (1,1) and (2,3) dots in the right figure are shown below. (1, 2) (2, 2) (3, 2) Note that the applied voltages are referenced to the common side drive voltage VM, and therefore displayed as VCOM-VSEG. Y3 VLCD = VCOM-VSEG (2, 3) (3, 3) Common (1, 3)
1 Common driver clock 1H VLCD
2
3
4
1
2
3
4
-VLCD
VLCD (2, 3) LCD applied voltage VM
-VLCD
Note) 1. When the LCD voltage applied to a dot is VLCD, it will be displayed as black in normally white mode and as white in normally black mode. 2. Since the drive waveform is dulled at the segment drive waveform transition and the actual voltage drops, this IC applies the compensation voltage at the drive waveform transition to compensate the actual voltage.
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(1, 1) LCD applied voltage VM
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MN863831EFS
I LCD Drive Voltage Names and Relationships (Reference)
The figure presents the LCD drive voltage provided by this IC and the MN8637 series common drivers, and the relationships between those voltages.
Logic supply voltage Segment/common (MN863831/MN86372)
Segment LCD drive voltage (MN863831)
Segment LCD drive waveforms
Common LCD Common LCD drive waveforms drive voltage (MN86372) VH(= 32 V)
VHC (= 4.2 V) VDD (= 3.0 V to 5.5 V) VH (= 3.9 V) VM (= 2.1 V) VL (= 0.3 V) VSS (= 0 V) VLC (= VSS = 0 V)
(/DISPOFF = high)
1. Absolute Maximum Ratings at VSS = 0 V, Ta = 25C Parameter Supply voltage 1 Supply voltage 2 Drive voltage Input voltage Operating temperature Storage temperature Symbol VDD
in
Rating Conditions
I Electrical Characteristics
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VL(= -27.8 V)
Unit V V V V C C
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VHC Vn VIN Topr Tstg
- 0.3 to +7.0 - 0.3 to +7.0
- 0.3 to VHC+0.3 - 0.3 to VDD+0.3 -20 to +75 -40 to +125
Note) 1. The absolute maximum ratings are limiting values for applied stresses below which the chip will not be destroyed. Operation is not guaranteed within these ranges. 2. These ratings are guarantees that apply when the standard Matsushita packages are used. 3. The term Vn above refers to VHC, VH, VM, VL, and VLC. These must be set up so that the following conditions hold: VHCVHVMVLVLC=VSS. 4. When power is first applied, certain voltage application sequences may result in large currents flowing in this IC and permanent damage to the IC. To prevent this, always apply the logic system power supply levels (VDD and VSS) first, and only after those levels are established apply the LCD drive system power supply levels. Note that the conditions in note 3 above must be met at all times during this process.
2. Operating Conditions at VSS = 0 V, Ta = -20C to 75C Parameter Supply voltage Drive voltage Drive voltage Drive voltage Drive voltage Symbol VDD VHC VH VM VL
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Min 2.5 3.0 Typ 3.3 4.2 0.3 Max 5.5 6.0 VHC VH 0.7 Unit V V V V V 17 VHC - 0.7 VHC - 0.3 VL 0
MN863831EFS
I Electrical Characteristics (continued)
2. Operating Conditions at VSS = 0 V, Ta = -20C to 75C (continued) Parameter Clock frequency Symbol fCP Cin tr, tf Conditions VDD = 2.5 V to 4.5 V VDD = 4.5 V to 5.5 V Digital signal input pin capacitance 1 Rise and fall time for CP, LP, and D0 to D11 At 1 MHz The following condition must be met: tr, tf1/2(1/f-2tw) Here, f is the frequency used and tw is the minimum pulse width.
Note) 1. 1: CP, D0 to D7 2. The VLC drive voltage is shorted to VSS internally to the IC. Thus VLC = VSS. 3. Connect directly each of the multiple drive supply pins of VHC, VH, VM, VL, and VLC.
Min 2.5 V to 4.5 V 4.5 V to 5.5 V
Typ 6
Max 30 55
Unit MHz MHz pF ns ns
3. DC Characteristics at VSS = 0 V, VDD = 2.5 V to 5.5 V, Ta = -20C to +75C Parameter Operating supply current Symbol IDD Conditions fCP = 20 MHz fDn = 10 MHz fLP = 36 kHz Min
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2 0.7 x VDD 0 -10 0.7 x VDD 0 30 0.7 x VDD 0 -10 -10 VDD- 0.5
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Typ Max 6 Unit mA 100 500 A A VDD 0.3 x VDD 10 V V A VDD 0.3 x VDD 300 V V K 100 VDD 0.3 x VDD 10 0.5 10 V V A V V A
Quiescent supply current (8-bit parallel input mode) Quiescent supply current (4-bit parallel input mode)
1) Input Pins (SHL, CP, LP, CL1, CL2, DF, D0 to D11, /DISPOFF) High-level input voltage Low-level input voltage Input leakage current VIH1 VIL1 ILI1
2) Input with Pull-up Resistor Pins (MOD) High-level input voltage Low-level input voltage Pull-up resistance 3) I/O Pins (/ER, /EL) High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Output leakage current VIH3 VIL3 ILI3 VOH3 VOL3 ILO3 IOH = - 0.5 mA IOL = 0.5 mA VIH2 VIL2 RPU2 VDD = 3.3 V, MOD = 0 V
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ISS1 ISS2
In the clock stopped state with MOD = open In the clock stopped state with MOD = low
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MN863831EFS
I Electrical Characteristics (continued)
3. DC Characteristics at VSS = 0 V, VDD = 2.5 V to 5.5 V, Ta = -20C to +75C (continued) Parameter Symbol Conditions Min Typ Max Unit
4) LCD Drive Outputs (O1 to O320) Output on resistance RON VHC = 4.2 V VH = 3.9 V VM = 2.1 V VL = 0.3 V VLC = 0.0 V Vn-VO = 0.5 V VO: Applied voltage of O1 to O320 Output on resistance Variations between drive voltages Output on resistance Variations between pins RON1 RON2 VHC = 4.2 V VH = 3.9 V VM = 2.1 V VL = 0.3 V VLC = 0.0 V
VSS = 0 V, VDD = 2.5 V, Ta = -20C to +75C VHC VH VM VL VLC 450 450 450 450 450 900 900 900 900 900

200 200

4. AC Characteristics at VSS = 0 V, VDD = 2.5 V to 5.5 V, Ta = -20C to +75C Parameter Symbol Conditions Min Typ Max 19 ns ns ns ns ns ns ns ns ns Unit
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tp
CP cycle time
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VDD(V) 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5 2.5 to 5.5 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5 2.5 to 4.5 4.5 to 5.5
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33.3 18 13 6 13 6 40 15 10 10 10 15 10 50 25 12 8 12 7 ns
CP low-level period
LP high-level period LP setup time 1
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LP setup time 2
LP hold time 1
LP hold time 2
Data setup time
Data hold time
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twcL twlH tst1 tst2 CP-LP CP-LP thd1 CP-LP thd2 tst3 CP-LP CP-Dx thd3 CP-Dx
CP high-level period
twcH
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MN863831EFS
I Electrical Characteristics (continued)
4. AC Characteristics at VSS = 0 V, VDD = 2.5 V to 5.5 V, Ta = -20C to +75C (continued) Parameter Symbol Conditions VDD(V) Carry signal setup time tst4 2.5 to 4.5 4.5 to 5.5 Carry signal output delay time td1 tlc1 tcl1 tcc tld 2.5 to 4.5 4.5 to 5.5 LP rising edge to CL2 rising edge time CL2 rising edge to LP falling edge time CL2 falling edge to CL1 rising edge time LP rising edge to DF rising edge time, DF falling edge time LCD drive signal output delay time 1 LCD drive signal output delay time 2 LCD drive signal output delay time 3 LCD drive signal output delay time 4 LCD drive signal output delay time 5 12 6 18 18 2 40 21 12 ns ns s ns ns ns Min Typ Max Unit
td2 td3 td4 td5 td6
LPOn CL1On CL2On DFOn
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/DISPOFFOn
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250 250 250 250 250
ns ns ns ns ns
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I Electrical Characteristics (continued)
4. AC Characteristics (continued) twcH 0.7 VDD 0.3 VDD tr 0.7 VDD 0.3 VDD tf tst2 0.7 VDD 0.3 VDD tr thd2 tw1H tst1 0.3 VDD twcL thd1 0.7 VDD 0.3 VDD tp
CP
LP
D0 to D7
Last data
in
0.3 VDD tf thd3 tst3 0.7 VDD 0.3 VDD 0.7 VDD 0.3 VDD tr , t f
SDF00018BEM
ar
First data 21
CP
0.3 VDD
D0 to D7
Pr
tr tr , t f
el
im
0.7 VDD
y
tf
MN863831EFS
I Electrical Characteristics (continued)
4. AC Characteristics (continued)
CP 0.3 VDD td1
When /EL and /ER are outputs tst4
0.3 VDD
0.3 VDD
CP
im el Pr
in
0.3 VDD td2 0.7 V[p-p] 0.3 V[p-p] O1 to O320 0.7 VDD CL1 0.3 VDD td3 0.7 V[p-p] O1 to O320 0.3 V[p-p]
22
SDF00018BEM
ar
When /EL and /ER are inputs
y
MN863831EFS
I Electrical Characteristics (continued)
4. AC Characteristics (continued)
0.7 VDD CL2 0.3 VDD td4 0.7 V[p-p] O1 to O320 0.3 V[p-p]
0.7 VDD DF 0.3 VDD
im el
0.7 VDD 0.3 VDD td6
SDF00018BEM
in
td5 0.7 V[p-p] 0.3 V[p-p] 0.7 V[p-p] 0.3 V[p-p] 23
O1 to O320
/DISPOFF
O1 to O320
Pr
ar
y
MN863831EFS
I Electrical Characteristics (continued)
4. AC Characteristics (continued)
0.7 VDD DF 0.3 VDD tld
0.7 VDD LP
tlc1
tcl1
CL2 0.3 VDD
im Pr el
SDF00018BEM
CL1
24
in
0.3 VDD
ar
tcc
0.7 VDD
y
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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